Semiconductor device with edge structure

ABSTRACT

A semiconductor device has an edge termination region ( 15 ) having a plurality of trenches ( 17 ). Conductive material ( 20 ) and insulating material ( 19 ) is formed at the trenches, and surface implants ( 21 ) are formed on either side of the trenches. A conductive bridge ( 23 ) connects the surface implants ( 21 ) to allow equilibrium to be reached in reverse bias.

The invention relates to a semiconductor device having an edgetermination, particularly an edge termination structure for ahigh-voltage semiconductor device, together with a method ofmanufacturing such a device.

Conventional reduced surface field (RESURF) semiconductor devices aremanufactured on a semiconductor substrate using epitaxial growth andimplantation processes. Such devices may be either vertical, in whichcurrent passes through the device substantially perpendicular to theplane of the semiconductor substrate or horizontal, i.e. with currentpassing through the device across the substrate.

A typical RESURF structure is a diode, transistor (such as a MOSFET), orthyristor having a region, often known as the drift region, that isdepleted in reverse bias at a voltage much less than breakdown.Increased reverse bias voltage will then lead to a relatively flat fieldprofile. This enables the structure to support a larger voltage acrossit without breaking down in reverse bias than would otherwise bepossible. This may be achieved, for example, by providing a plurality ofp-type regions in an n-type drift region so that in reverse bias thedepletion region of the p-n junctions includes substantially the wholeof the drift region. Thus, RESURF structures may be used in high voltageapplications.

For vertical RESURF structures, deep p-n junctions are required and itcan be more convenient to manufacture these using a trench etch process,avoiding the need for multiple epitaxy. Some other advantages may beobtained using a trench structure. These may include smaller pitch sizesdue to a lower thermal budget which lowers the breakdown voltage atwhich vertical RESURF devices become attractive, and which also offerlower specific resistances. Trench etching can potentially result in acheaper process with less processing steps.

The trenches in the active areas of multiple RESURF devices withtrenches may be discrete columns extending into the substrate, stripesor close-packed shapes, for example, hexagonal or square latticepatterns of trenches. In many cases, better results are obtained using astripe or close-packed design than is obtained by using columns, sincesuch designs offer better RESURF at the same pitch, i.e. the samespacing between trenches.

The skilled person will be aware of many structures that also suitableat high voltages, not just RESURF structures.

For high voltage devices, a proper edge termination is required.Otherwise, the high voltages required may cause electrical breakdown inthe edge region of the semiconductor device.

A number of edge termination structures have been proposed. For example,WO 99/23703 (Siemens A G) discloses the use of a number of p⁻ guardrings provided in trenches in an n⁻ epitaxial layer.

An alternative structure is taught in EP 1011146 (ST MicroelectronicsSrl), which discloses an integrated edge structure having p implants atdifferent depths to form the edge termination structure. It is alsopossible to provide an additional implant at the surface to preventdepletion of the top of the p-type regions.

However, these prior art solutions rely on a very accurate dopingconcentration profile, laterally as well as horizontally, as the ideainvolves depleting the whole of the edge structure by choosing thedopant distribution so that the electric field does not exceed thecritical field anywhere. Such a very accurate doping concentrationprofile is of course difficult to achieve in practice, and raises thecost of the device.

According to the invention there is provided a semiconductor body havingopposed first and second surfaces and an edge termination region at theperiphery of the semiconductor body; a plurality of edge terminationtrenches extending across the edge termination region of thesemiconductor body and vertically from the first surface towards thesecond surface of the semiconductor body through a region of a firstconductivity type; conductive material extending vertically at the edgetermination trenches for depleting the region of a first conductivitytype between adjacent trenches; insulating material extending verticallyat the edge termination trenches; surface implants of secondconductivity type opposite to the first conductivity type extendingparallel to and along both sides of the edge termination trenchesadjacent to the first surface; and an electrically conductive pathassociated with each edge termination trench forming an electricalconnection between the surface implants on both sides of the edgetermination trench.

The use of stripe or close-packed RESURF structures in the active regionof a semiconductor device makes it difficult to build an edgetermination out of column-like structures because the column-likestructures would need to be closer together or have overly wide trenchregions due to the fact that RESURF effect is much less with columns.Thus, it is preferable that the RESURF structures in the edgetermination extend laterally across the edge termination region.

The inventors have however realised that there is a problem withlaterally extending insulated trenches as the edge terminationstructure. As will be explained below, for the edge terminationstructure to work properly, it is necessary for charge to be transferredbetween the p-n junction formed on one side of the trench with the p-njunction on the other side of the trench. Accordingly, the inventorshave realised that when using insulated trenches, it is necessary toprovide an electrically conductive path between the two sides of thetrench for the structure to work properly.

In embodiments of the invention, the semiconductor body has a centralactive device region, and the edge termination region surrounds thecentral active device region.

The plurality of edge termination trenches may have different depths,the trenches adjacent to the central region of the semiconductor devicebeing deeper than the trenches adjacent to the periphery.

Preferably, the conductive material extending vertically at the trenchesis of the second conductivity type.

The electrically conductive path may be formed by a conductive layerfilling at least the portion of the edge termination trenches adjacentto the first surface. Alternatively, the electrically conductive pathmay be formed by a conductive layer extending over the first surfacetransversely across the edge termination trenches between the surfaceimplants on both sides of the edge termination trenches.

The electrically conductive path may be of doped polysilicon, metal, orother suitable material. Doped polysilicon is particularly suitable.

In embodiments, the conductive material is a conductive layer on thesidewalls of the edge termination trenches extending downwards from thesurface implants on both sides of the trench; and the insulatingmaterial fills the trenches between the conductive layers on the sidesof the trench.

In alternative embodiments, the insulating material is an insulatinglayer extending downwards on the sidewalls of the edge terminationtrenches; the conductive material fills the trench between theinsulating material on the sidewalls.

The invention also relates to a method of manufacturing a semiconductordevice, including providing a semiconductor body having opposed firstand second surfaces and a semiconductor region of first conductivitytype adjacent to the first surface; forming trenches extending laterallyacross the semiconductor body and vertically from the first surfacetowards the second surface; filling the trenches with insulatingmaterial; forming conducting semiconductor regions of secondconductivity type opposite to the first conductivity type along bothsides of the trenches; and depositing conductive material on the firstsurface at the trenches to form a conductive path between the conductingsemiconductor regions on both sides of the trenches.

The invention will now be described, purely by way of example, withreference to the accompanying drawings, in which:

FIG. 1 shows a side view through a structure in accordance with theinvention;

FIG. 2 shows a top view of a structure according to FIG. 1;

FIG. 3 illustrates the charge patterns in edge depletion structures;

FIG. 4 shows the results of a numerical simulation of an edgetermination scheme using such a floating ring structure;

FIG. 5 shows alternative methods of connecting both sides of the surfaceimplants;

FIG. 6 shows alternative trench filling approaches; and

FIG. 7 shows an further embodiment of the invention having trenches ofdifferent depths.

Referring to FIGS. 1 and 2, an n-type semiconductor substrate 1 has ann⁻ type epitaxial layer 3 deposited on one side. These two layers form asemiconductor body 9 having first and second surfaces: the secondsurface 7 is formed by the rear of the semiconductor substrate 1 and thefirst surface 5 formed by the top of the epitaxial layer 3.

The central active device region 11 on the semiconductor body 9 isformed with active vertical device structures in a manner well known tothe person skilled in the art. In the specific embodiment disclosed, avertical RESURF structure having trenches 70 is provided. Between thecentral region 11 and the peripheral edge 13 of the semiconductor body9, is provided the edge termination region 15 which has the edgetermination structure of the present invention.

A plurality of trenches 17 extend laterally (see FIG. 2) across thefirst surface 5 of the semiconductor body 9 around the central region11. As may be seen from FIG. 2, the trenches surround the central region11. The side walls 18 of the trenches are doped p-type to formconductive layer 20. The trenches are filled with insulated dielectricmaterial 19. It should be noted that the term conductive material isused in this specification to mean material that can conduct, and thusincludes semiconducting and resistive material.

P-type surface implants 21 extend parallel to the trenches across thefirst surface 5 of the semiconductor body, a pair of p-type surfaceimplants 21 surrounding each insulated trench 17. A doped polysiliconconductive bridge 23 connects the p-type surface implants 21 across eachtrench 17. The trenches 17 define n-type regions 31 between adjacenttrenches.

For clarity, the bridge 23 is omitted from FIG. 2 to allow thedielectric filling 19 and the surface implants 21 to be seen. Further,in view of the scale of FIG. 2, the p-type material 20 between thedielectric layer 19 and the surface implants 23 is also not shown, andonly two trenches 17 are shown though in reality there may be more.

Front 25 and rear 27 contacts are provided on the first surface in theactive region and on the second surface respectively of thesemiconductor device to form a vertical semiconductor device.

The manufacture of the device may proceed by providing epitaxial layer 3on substrate 1, and then forming a pattern of trenches 17 extending fromthe front surface 5 of the epitaxal layer 3 through epitaxial layer 3towards the rear face 7. A thin p-type layer 20 is formed on thesidewalls of the trenches 17 by diffusing boron into the siliconsidewall. The trenches are then filled by the dielectric 19.Alternatively, the trenches can be filled with doped oxide and boronimplanted or diffused into the silicon. Alternative dopants may also beused.

P-type surface implants 21 are then formed by ion implantation. Althoughnot shown, this step may also deposit a p-type layer in the activeregion 11 to form a p-n semiconductor diode. Doped polysilicon 23 isthen formed to connect adjacent surface implants 21.

Front and rear contacts 25,27 are then formed.

In use, with 0V applied to the front contact 25, the semiconductordevice needs to withstand a large positive voltage on rear contact 27.The p-type material 20 causes depletion of the adjacent n-type regions31 of the epitaxial layer in order that vertical breakdown does notoccur.

The edge termination structure in the edge termination region 15 isdesigned to avoid breakdown in the edge region. The voltage drop betweenadjacent trench rings 17 is determined by the voltage required todeplete the n-type regions 31 between adjacent trenches.

In detail, referring to FIG. 3, the surface implants 21 in conjunctionwith regions 31 define forward bias p-n junctions 33 and reverse biasp-n junctions 35. Impact ionisation generates electron-hole pairs 39which cause a small hole current at the reverse junctions 35. The exactbias of the floating p-type region 21 is determined by the conditionthat this hole current equals the hole flow across the forward-biasedp-n junctions 33, to avoid hole build up in the surface implant regions21.

Thus, if the conductive path 23 between the surface implants 21 oneither side of the trench were not present, holes generated at thereverse junction 35 would not pass to the forward junction 33. Theinventors have realised that this would mean that the mechanism forobtaining equilibrium simply cannot take place. Thus, the provision ofthe conductive path defined by metallisation 23 allows the edgetermination structure to work properly.

Thus, the arrangement according to the invention allows edge terminationstructures to be used also for stripe or close-packed trench designs, byovercoming a problem that would otherwise occur with these designs.These designs are of particular commercial interest, since they offerbetter RESURF at the same pitch.

The effectiveness of the invention is illustrated in FIG. 4, whichillustrates calculated values of the potential drop in the edge region15. A very gentle potential drop is shown to be achieved.

There are a number of possibilities to connect the surface implants 21on both sides of the trench 17. FIG. 5 a illustrates an approach inwhich the top of the dielectric 19 and p-type filling is etch back andthe top of the trench then filled with doped polysilicon 41. In FIG. 5b, an alternative approach is described where metal 43 forms a bridgeacross the trench between surface implants 21 instead of the dopedpolysilicon 23 used in the arrangement shown in FIG. 1.

An alternative method of forming an insulated trench is illustrated inFIG. 6. Dielectric 62 is grown on the sidewalls 18 of the trench 17 andthen the trench is filled with p-doped polysilicon 60.

The invention is also applicable to the type of RESURF device havingresistive material contained in a trench separated from an adjacentdrift region by an insulating layer.

The invention is not restricted to the aforementioned types of RESURFdevice. For example, the invention is also applicable to devices using adeep trench lined with relatively thick oxide (200–400 nm) and filledwith highly doped polysilicon or metal acting as a field plate. Suchdevices are known, for example from U.S. Pat. No. 5,365,102 (Mehrotra).

A further embodiment of the invention, shown in FIG. 7, differs fromthat shown in FIG. 1 in that the depth of the trenches 17 adjacent tothe central region 11 of the semiconductor device are deeper than thetrenches adjacent to the periphery 13 of the semiconductor device.

This can reduce the total size of the edge termination region byallowing more volts to be dropped across the outer part of the edgetermination region than would otherwise be the case. Where the trenchesat the periphery of the edge termination region have the same structureas the trenches at the centre or the edge termination region, theproperties and spacing of the trenches need to be determined by thehigher electrical field present in the portion of the edge terminationregion adjacent to the central region, which causes the voltage droppedagainst the more peripheral paths of the edge termination region to besignificantly less than the maximum obtainable.

Thus, the structure of FIG. 7 can save silicon real estate as comparedwith the structure of FIG. 1.

From reading the present disclosure, other variations and modificationswill be apparent to persons skilled in the art. Such variations andmodifications may involve equivalent and other features which arealready known in the design, manufacture and use of semiconductordevices and which may be used in addition to or instead of featuresdescribed herein. Although claims have been formulated in thisapplication to particular combinations of features, it should beunderstood that the scope of disclosure also includes any novel featureor any novel combination of features disclosed herein either explicitlyor implicitly or any generalisation thereof, whether or not it mitigatesany or all of the same technical problems as does the present invention.The applicants hereby give notice that new claims may be formulated toany such features and/or combinations of such features during theprosecution of the present application or of any further applicationsderived therefrom.

The skilled person will realise that although the invention has beendescribed for a device having a particular arrangement of n-type andp-type regions, these may be reversed.

The invention is applicable to semiconductor structures made of silicon,gallium arsenide, and any other semiconductor material.

The arrangement in the active region 11 may be varied as requireddepending on the desired structure—it is not essential that the activeregion is also a RESURF structure. However, the invention is ofparticular benefit in trench or close-packed RESURF structures.

1. A semiconductor device with an edge termination structure,comprising: a semiconductor body having opposed first and secondsurfaces and an edge termination region at the periphery of thesemiconductor body; a plurality of edge termination trenches extendingacross the edge termination region of the semiconductor body andvertically from the first surface towards the second surface of thesemiconductor body through a region of a first conductivity type;conductive material extending vertically at the edge terminationtrenches for depleting the region of a first conductivity type betweenadjacent trenches; insulating material extending vertically at the edgetermination trenches; surface implants of second conductivity typeopposite to the first conductivity type extending parallel to and alongboth sides of the edge termination trenches adjacent to the firstsurface; and an electrically conductive path associated with each edgetermination trench forming an electrical connection between the surfaceimplants on both sides of the edge termination trench.
 2. Asemiconductor device according to claim 1 wherein the conductivematerial extending vertically at the trenches is semiconductor materialof the second conductivity type.
 3. A semiconductor device according toclaim 1 or 2 wherein the electrically conductive path is formed by aconductive layer filling at least the portion of the edge termination,trenches adjacent to the first surface.
 4. A semiconductor deviceaccording to claim 1 or 2 wherein the electrically conductive path isformed by a conductive layer extending over the first surfacetransversely across the edge termination trenches between the surfaceimplants on both sides of the edge termination trenches.
 5. Asemiconductor device according to claim 1, wherein the edge terminationtrenches have sidewalls; the conductive material is a conductive layeralong the sidewalls of the edge termination trenches extending downwardsfrom the surface implants on both sides of the trench; and theinsulating material fills the trenches between the conductive layers onthe sides of the trench.
 6. A semiconductor device according to claim 1,wherein the edge termination trenches have sidewalls; the insulatingmaterial is an insulating layer extending downwards on the sidewalls ofthe edge termination trenches; the conductive material fills the trenchbetween the insulating material on the sidewalls.
 7. A semiconductordevice according to claim 1, wherein the electrically conductive path isof doped polysilicon.
 8. A semiconductor device according to claim 1,wherein: the semiconductor body has a central active device region and aperiphery; the edge termination region surrounds the central region ofthe semiconductor device within the periphery; and the plurality oftrenches have different depths, the trenches adjacent to the centralregion of the semiconductor device being deeper than the trenchesadjacent to the periphery.
 9. A semiconductor device according to claim1, wherein the semiconductor device has an active device regionincluding a plurality of active region trenches extending laterallyacross the active device region and vertically from the first surfacetowards the second surface.
 10. A method of manufacture of asemiconductor device, including providing a semiconductor body, havingopposed first and second surfaces and a semiconductor region of firstconductivity type adjacent to the first surface; forming trenchesextending laterally across the semiconductor is body and vertically fromthe first surface towards the second surface; forming verticallyextending conductive material and insulating material at each of thetrenches; forming conducting semiconductor regions of secondconductivity type opposite to the first conductivity type along bothsides of the trenches in an edge termination region; and depositingconductive material on the first surface at the trenches to form aconductive path between the conducting semiconductor regions on bothsides of the trenches.